module FSMC(
    ab,   //address bus
    db,    //data bus
    wrn,    //wr
    rdn,    //rd
    resetn, //resetn
    csn,    //cs
    ina,    //input data a
    inb,    //input data b
    inc,    //input data c
    ind,    //input data d
    ine,    //input data e
    inf,    //input data f
    ing,    //input data g
    inh,    //input data h
    outa,    //output data a
    outb,    //output data a
    outc,    //output data a
    outd,    //output data a
    oute,    //output data a
    outf,    //output data a
    outg,    //output data a
    outh     //output data a
    );
    
    input[2:0]  ab;
    inout[15:0] db;
    input wrn;
    input rdn;
    input resetn;
    input csn;
    input [15:0] ina;
    input [15:0] inb;
    input [15:0] inc;
    input [15:0] ind;
    input [15:0] ine;
    input [15:0] inf;
    input [15:0] ing;
    input [15:0] inh;
    
    output reg [15:0] outa;
    output reg [15:0] outb;
    output reg [15:0] outc;
    output reg [15:0] outd;
    output reg [15:0] oute;
    output reg [15:0] outf;
    output reg [15:0] outg;
    output reg [15:0] outh;
    
    wire rd;
    wire wr;
    
    reg [15:0] indata;
    
    assign rd = !(csn & rdn); //get rd pulse  ____|~~~~|______
    assign wr = !(csn & wrn); //get wr pulse  ____|~~~~|______
    
    assign db = rd ? indata:16'hzzzz;
    
    
    //write data, 根据地址线选择八个空间写入，每个空间16位
    always @(posedge wr or negedge resetn)
    begin
        if(!resetn)begin
            outa <= 16'h0000;
            outb <= 16'h0000;
            outc <= 16'h0000;
            outd <= 16'h0000;
            oute <= 16'h0000;
            outf <= 16'h0000;
            outg <= 16'h0000;
            outh <= 16'h0000;
        end
		  else  
		  begin
			  case (ab)            
					3'b000:outa <= db;
					3'b001:outb <= db;
					3'b010:outc <= db;
					3'b011:outd <= db;
					3'b100:oute <= db;
					3'b101:outf <= db;
					3'b110:outg <= db;
					3'b111:outh <= db;
					default:;
			  endcase
        end
    end
    
            
    //read data 根据地址线选择8个空间读取，每个空间 16位
    always @(posedge rd or negedge resetn)
    begin
        if(!resetn)indata <= 16'h0000;
        else  begin
        case (ab)
            3'b000:indata <= ina;
            3'b001:indata <= inb;
            3'b010:indata <= inc;
            3'b011:indata <= ind;
            3'b100:indata <= ine;
            3'b101:indata <= inf;
            3'b110:indata <= ing;
            3'b111:indata <= inh;
            default:;
        endcase
        end
    end
    
endmodule

